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fn9256 rev 0.00 page 1 of 12 march 7, 2006 fn9256 rev 0.00 march 7, 2006 isl6273 1.2a low quiescent current 1.5mhz high efficiency synchronous b uck regulator datasheet isl6273 is a 1.2a, 1.5mhz step-down regulator, which is ideal for powering low-voltage microprocessors in compact devices such as pdas and cell ular phones. it is optimized for generating low ou tput voltages down to 0.8v. the supply voltage range is from 2.7v to 5.5v allowing the use of a single li+ cell, three nimh cells or a regulated 5v input. it has guaranteed minim um output current o f 1.2a. 1.5mhz pulse-width modulation (pwm) switching frequency allows using small external components. it has flexible operation mode selection of forced pw m mode and low iq mode with as low as 25 ? a quiescent current for highest light load efficiency to maximize battery life. the isl6273 includes a pair o f low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mv dropout voltage at 1.2a. the isl6273 offers a 200ms p ower-on-reset (por) timer at power up. the timer outpu t can be reset by rsi. when shutdown, isl6273 discharges the output capacitor. other features include internal digit al soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. the isl6273 is offered in a 10 ld 3x3mm dfn package with 1mm maximum height. the complete converter occupies less than 1 cm 2 area. features ? high efficiency synchronous buck regulator with up to 95% efficiency ? 200ms reset timer ? discharge output cap when shutdown ? 2.7v to 5.5v supply voltage ? 3% output accuracy over temperature/load/line ? 1.2a guaranteed output current ?25 ? a quiescent supply current in iq mode ? selectable forced pwm mode and iq mode ? less than 1 ? a logic controlled shutdown current ? 100% maximum duty cycle for lowest dropout ? internal loop compensation ? internal digital soft-start ? peak current limiting, s hort circuit protection ? over-temperat ure protection ? enable ? small 10 ld 3x3mm dfn ? pb-free plus anneal available (rohs compliant) applications ? single li-ion battery-powered equipment ? dsp core power ? pdas and palmtops pinout isl6273 (10 ld 3x3 dfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6273IRZ 273z -40 to 85 10 ld 3x3 dfn l10.3x3c ISL6273IRZ-t 273z -40 to 85 10 ld 3x3 dfn l10.3x3c note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/d ie attach materials and 100% matte tin plate termination finish, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. pvin vcc en por mode phase pgnd sgnd fb rsi 2 3 4 1 5 9 8 7 10 6 n o t r e c o m m e n d e d f o r n e w d e s i g n s p o s s i b l e s u b s t i t u t e p r o d u c t i s l 9 1 0 6
isl6273 fn9256 rev 0.00 page 2 of 12 march 7, 2006 absolute maximum rati ngs (reference to sgnd) thermal information supply voltage (pvin, vcc) . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v en, rsi, mode, phase, por . . . . . . . . . . . . . -0.3v to vcc +0.3v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v recommended operating conditions pvin supply voltage range . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.2a ambient temperature range . . . . . . . . . . . . . . . . . . . .-40c to 85c thermal resistance (notes 1, 2) ? ja (c/w) ? jc (c/w) 3x3 dfn package . . . . . . . . . . . . . . 44 5.5 junction temperature range. . . . . . . . . . . . . . . . . . . -40c to 125c storage temperature range . . . . . . . . . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. ? jc , case temperature location is at the center of the exposed m etal pad on the package underside. see tech brief tb379. electrical specifications unless otherwise noted, all parameter limits are guaranteed ove r the recommended operating conditions and the typical specification are measured at the following conditi ons: t a = 25c, v pvin = v vcc = 3.6v, en = vcc, rsi = 0v, mode = vcc, l = 1.8 ? h, c1 = 10 ? f, c2 = 10 ? f, i out = 0a (see the typical application circuit). parameter symbol test conditions min typ max units supply vcc undervoltage lockout threshold v uvlo rising - 2.5 2.7 v falling 2.2 2.4 - v quiescent supply current i pvin mode = vcc, no load at the output - 25 50 ? a mode = sgnd, no load at the output - 5 8 ma shut down supply current i sd vcc = pvin = 5.5v, en = low - 0.1 2 ? a output regulation fb regulation voltage v fb t a = 0c to 85c 0.784 0.8 0.816 v t a = -40c to 85c 0.78 0.8 0.82 v fb bias current i fb fb = 0.75v - 0.1 - ? a output voltage accuracy pvin = v o + 0.5v to 5.5v, io = 0 to 1.2a , t a = -40c to 85c -3 - 3 % line regulation pvin = v o + 0.5v to 5.5v (minimal 2.7v) - 0.2 - %/v maximum output current 1.2 - - a compensation error amplifier trans-conductance a djustable version, design inf o only - 20 - ? a/v phase p-channel mosfet on resistance pvin = 3.6v, io = 200ma - 0.12 0.22 ? pvin = 2.7v, io = 200ma - 0.16 0.27 ? n-channel mosfet on resistance pvin = 3.6v, io = 200ma - 0.11 0.22 ? pvin = 2.7v, io = 200ma - 0.15 0.27 ? p-channel mosfet peak current limit i pk 1.5 2.1 2.6 a phase maximum duty cycle - 100 - % pwm switching frequency f s t a = -40c to 85c 1.35 1.5 1.75 mhz phase minimum on time mode = low (forced pwm mode) - - 140 ns soft start-up time - 1.1 -ms
isl6273 fn9256 rev 0.00 page 3 of 12 march 7, 2006 por output low voltage sinking 1ma, fb = 0.7v - - 0.3 v delay time 150 200 275 ms por pin leakage current por = vcc = 3.6v - 0.01 0.1 ? a minimum supply voltage for valid por signal 1.2 - - v internal pgood low rising thres hold percentage of nominal regula tion voltage 89.5 92 94.5 % internal pgood low falling threshold percentage of nominal regul ation voltage 85 88 91 % internal pgood high rising threshold percentage of nominal regul ation voltage 105.5 108 110.5 % internal pgood high falling thre shold percentage of nominal regu lation voltage 102 105 108 % internal pgood delay time -50- ? s en, mode, rsi logic input low --0.4v logic input high 1.4 - - v logic input leakage current pulled up to 5.5v - 0.1 1 ? a thermal shutdown - 150 - c thermal shutdown hysteresis -25-c electrical specifications unless otherwise noted, all parameter limits are guaranteed ove r the recommended operating conditions and the typical specification are measured at the following conditi ons: t a = 25c, v pvin = v vcc = 3.6v, en = vcc, rsi = 0v, mode = vcc, l = 1.8 ? h, c1 = 10 ? f, c2 = 10 ? f, i out = 0a (see the typical application circuit). parameter symbol test conditions min typ max units
isl6273 fn9256 rev 0.00 page 4 of 12 march 7, 2006 typical operating performance figure 1. efficieny vs load current (v in = 3.6v) figure 2. v out vs load current (v in = 3.6v) figure 3. efficiency vs load current (v o = 1.8v) figure 4. v out vs load current (v in = 2.7v) figure 5. i q vs v in (pfm) figure 6. i q vs v in (pwm) v o = 2.5v v o = 1.2v 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) efficiency (%) v o = 2.8v 3.3 3.31 3.32 3.33 3.34 3.35 3.36 3.37 0.1 1 10 100 1000 load current (ma) v out (v) v in = 3.6v 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) efficiency (%) v in = 2.7v 1.74 1.76 1.78 1.8 1.82 1.84 0.1 1 10 100 1000 load current (ma) v out (v) v in = 2.7v 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 2.9 3.4 3.9 4.4 4.9 5.4 v in voltage range (2.9v-5.5v) input current (ma) input current in pfm mode of 2.8v 0 1 2 3 4 5 6 7 2.9 3.4 3.9 4.4 4.9 5.4 v in voltage range (2.9v-5.5v) input current (ma) input current in pwm mode of 2.8v
isl6273 fn9256 rev 0.00 page 5 of 12 march 7, 2006 figure 7. switching frequency vs v in figure 8. line regulation (i o = 1a) figure 9. load regulation (v in = 3.6v in pwm mode) figure 10. soft-start figure 11. pfm mode (v in = 3v; v o = 1.6v; i o = 50ma) figure 12. steady-state in pwm mode (v in = 3.6v; v o = 1.6v; i o = 1a) typical operating performance (continued) 1.57 1.575 1.58 1.585 1.59 1.595 1.6 1.605 2.7 3.2 3.7 4.2 4.7 5.2 v in (v) switching frequency (mhz) 1.6 1.602 1.604 1.606 1.608 1.61 2.7 3.7 4.7 v in (v) v o (v) 1.59 1.595 1.6 1.605 1.61 0 200 400 600 800 1000 i o (ma) v o (v)
isl6273 fn9256 rev 0.00 page 6 of 12 march 7, 2006 pin descriptions pvin input supply voltage. connect a 10 ? f ceramic capacitor to power ground. vcc supply voltage for internal analog and digital control circuits , delivered from pvin. bypass with 0.1 ? f ceramic capacitor to signal ground. en regulator enable pin. enable the output when driven to high. shutdown the chip and discharge output capacitor when driven to low. do not leav e this pin floating. por 200ms timer output. at power up or en hi, this output is a 200ms delayed power-good signa l for the outpu t voltage. this output can be re set by a low rsi signal. 200ms starts when rsi goes to high. mode mode selection pin. connect to logic high or input voltage vcc for low iq mode; connect to logic low or ground for forced pwm mode. do not l eave this pin floating. phase switching node connection. co nnect to one terminal of inductor. pgnd power ground. connect all power grounds to this pin sgnd analog ground. sg nd and pgnd shoul d only have one point connection. fb buck regulator out put feedback. connec t to the output through a resistor divider fo r adjustable output voltage (isl6273-adj). for preset output voltage, connect this pin to the output. rsi this input resets the 200ms ti mer. when the output voltage is within the pgood window, an internal timer is started and generates a por signal 200ms later when rsi is low. a low rsi resets por and rsi high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is re set by the output voltage condition. exposed pad the exposed pad must be conne cted to the pgnd pin for proper electrical performanc e. the exposed pad must also be connected to as much as po ssible for optimal thermal performance. figure 13. transient load test (pfm & pwm v in = 3.6v; v o = 1.6v; i o = 0a~1a) figure 14. load transient in pwm mode (v in = 3.6v; v o = 1.6v; i o = 0a~1a) typical operating performance (continued)
isl6273 fn9256 rev 0.00 page 7 of 12 march 7, 2006 typical applications figure 15. typical applicatio n for fixed output version c2 10f l phase pgnd sgnd fb rsi pvin vcc en por mode input 2.7v-5.5v output 2.5v/1.2a c1 10 f vcc r1 100k c3: 0.1f isl6273 - 25 1.8uh parts description manufacturers p art number specifications size l output inductor sumida cdrh4d18 2r2 2.2 ? h/1.32a/58m ? 5.0 ? 5.0 ? 2.0mm coilcraft 1008ps-182m 1.8h/1.9a/90m ? 3.8x3.8x2.8mm c1 input capacitor murata grm21br60j106ke19l 10 ? f/6.3v/3m ? 2.0x1.25x1.25mm (0805) c3 bypass capacitor taiyo yuden emk107bj104ma 0.1 ? f/16v 1.6x0.8x0.8mm (0603) c2 output capacitor murata grm21br60j106ke19l 10 ? f/6.3v/3m ? 2.0x1.25x1.25mm (0805) r1 pull-up resistor various 100k ? 1.6x0.8x0.45mm (0603) figure 16. typical application for adjustable version l phase pgnd sgnd fb rsi pvin vcc en por mode input 2.7v-5.5v output 1.3v/1.2a c1 10uf vcc r1 100k c3: 0.1f isl6273 - adj 1.8uh c2 10uf r2 100k r3 160k
fn9256 rev 0.00 page 8 of 12 march 7, 2006 isl6273 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. block diagram figure 17. functional block diagram note 1: for adjustable output version, t he internal feedback resistor d ivider is disabled and the fb pin is directly connected to the error amplifier. phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd oscillator oscillator zero -cross sensing 5 ? vcc + note 1 bandgap scp + 0.2v en shutdown 200ms delay sgnd 0.8pf 25pf 400k phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd oscillator oscillator zero -cross sensing 5 ? vcc + oscillator oscillator zero -cross sensing 5 ? vcc + note 1 bandgap scp + 0.2v en shutdown 200ms delay sgnd 0.8pf 25pf 400k phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd oscillator oscillator zero -cross sensing 5 ? vcc + oscillator oscillator zero -cross sensing 5 ? vcc + note 1 bandgap scp + 0.2v en shutdown 200ms delay sgnd 0.8pf 25pf 400k phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v note 1 bandgap scp + 0.2v en shutdown 200ms delay sgnd 0.8pf 25pf 400k phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd phase + + csa1 + + ocp 1v 0.2v skip + + + slope comp slope comp soft start soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb + 0.736v 0.864v por mode shutdown pvin pgnd por mode shutdown pvin pgnd oscillator oscillator zero -cross sensing 5 ? vcc + oscillator oscillator zero -cross sensing 5 ? vcc + oscillator oscillator zero -cross sensing 5 ? vcc + note 1 bandgap scp + 0.2v en shutdown 200ms delay sgnd 0.8pf 25pf 400k rsi 5 ?
isl6273 fn9256 rev 0.00 page 9 of 12 march 7, 2006 theory of operation the isl6273 is a step -down switching regulator optimized for battery-powered handheld appl ications. the regulator operates at 1.5mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at lig ht load, the regulator reduces t he switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery lif e. the quiescent current when the output is not loaded is typically only 25 ? a. the supply current is typically only 0.1 ? a when the regulator is shut down. the isl6273 has four fixed outp ut voltage versions and one adjustable version. pwm control scheme the isl6273 employs the current-mode pulse-width modulation (pwm) cont rol scheme for fast transient response and pulse-by-pulse current limit ing. figure 17 shows the block diagram. the current loop consis ts of the oscillator, the pwm comparator comp, current sens ing circuit, and the slope compensation for the current loop stability. the current sensin g circuit consists of t he resistance of t he p-channel mosfet when it is turned on and the curr ent sense amplifier csa. the gain for the current sensing circ uit is typically 0.4v/a. the control reference for the curr ent loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initial ized by the clock from the oscillator. the p-channel mo sfet is turned on at the beginning of a pwm cycle and the curren t in the mosfet starts to ramp up. when the su m of the current amplifier csa and the compensatio n slope (0.675v/ ? s) reaches th e control reference of the current loop , the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-c hannel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 18 shows the typical operati ng waveforms during the pwm operation. the dotted lines illustrate the sum of the compensation ramp and the c urrent-sense amplifier csa output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the volta ge control loop. the feedback signal comes from the fb pin. th e soft-start block only affects the operation during the st art-up and will be discussed separately shortly. the error am plifier is a transconductance amplifier that converts the vo ltage error signal to a current output. the voltage loop is internally compensated with the 30pf and 300k ? rc network. the maximum eamp voltage output is precisely clamped t o the bandgap voltage (1.172v). skip mode the isl6273 enters a pulse-ski pping mode at light load to minimize the switching loss by reducing the effective switching frequency. figure 19 illustrates the skip-mode operation. a zero-cross sensing circuit show n in figure 17 monitors the n- mosfet current for zero crossing. when 8 consecutive cycles of the n-mosfet crossing zero are detected, the regulator enters the skip mode. during the 8 detecting cycles, the current in the inductor is al lowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. figure 18. pwm operation waveforms v eamp v csa1 duty cycle i l v out figure 19. skip mode operation waveforms clock i l v out nominal + 1.5% nominal current limit load current 0 8 cycles
isl6273 fn9256 rev 0.00 page 10 of 12 march 7, 2006 once the skip mode i s entered, the pulse modulation starts being controlled by the skip comparator s hown in figure 17. each pulse cycle is still synch ronized by the pwm clock. the n-mosfet is turned on at the clock and turned off when its current reaches 20% of the current limit value (0.2v at the csa output). as the average inductor current in each cycle is highe r than the average curr ent of the load, the output voltage rises cycle over cycle. when the output voltage reaches 1.5% above the nominal voltage, the p-mosf et is turned off immediately. then the inductor current is fu lly discharged to zero and stays at zero. the output voltage reduc es gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal v oltage, the p-mosfet will be turned on again at the clock, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% bel ow the nominal voltage. mode control the isl6273 has a mode pin th at controls the operation mode. when the mode pin is dr iven to low or shorted to ground, the regulator operates in a forced pwm mode. the forced pwm mode remains the fixed pwm frequency at light load instead of entering the skip mode. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 17. the current sensing circuit has a gain of 0.4v/a, from the n-mosfet current to the c sa output. when t he csa output reaches 1v, which is equivalent t o 2.5a for the switch current, the ocp comparator is tripped to turn off the p-mosfet immediately. short-circuit protection a short-circuit protection scp c omparator monitors the fb pin voltage for output short-circuit protection. when the fb is low er than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start-up or an output short-circ uit event. por signal the isl6273 offers a power-on reset (por) signal for resetting the microprocessor at the power up. when the output voltage is not within a pow er-good window, the por pin outputs an open-drain low signal to reset the microprocessor. the output voltage is monitored through the fb pin. f or the fixed output voltage versions, the monitori ng node is the center of the resistive voltage divider. for the adjustable version, the fb p in voltage is monitored direct ly. when the voltage of the monitored node is within the wi ndow of 0.736v and 0.864v, a power-good signal is issued to turn off the open-drain por pin. the rising edge of t he por output is de layed by 200ms. rsi signal the rsi signal is a reset input c ontrol for the por signal. the power-good signal is gated by t he rsi signal, as shown in figure 17. when the rs i is high, the por signal will remain low, independent on the power good signal. uvlo when the input voltage is bel ow the undervoltage lock out (uvlo) threshold, the regulator is disabled. soft start-up the soft start-up eliminates the inrush current during the star t- up. the soft start b lock outputs a ramp re ference to both the voltage loop and the current l oop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the out put voltage rises in a controlled fashion. at the very beginning of the start-up, the ou tput voltage is le ss than 0.2v; henc e the pwm operating fr equency is 1/3 of the normal frequency. figure 10 shows the start-up waveforms. power mosfets the power mosfets are optimized for best efficiency. the on resistance for the p-mosfet is typically150m ? and the on resistance for the n-mo sfet is typically 150m ? . 100% duty cycle the isl6273 features 100% dut y cycle operation to maximize the battery life. when the battery voltage drops to a level tha t the isl6273 can no longer mai ntain the regu lation at the output, the regulator completel y turns on the p-mosfet. the maximum drop out voltage u nder the 100% duty-cycle operation is the product of t he load current and the on resistance of the p-mosfet. enable the enable (en) input allows use r to control the turning on or off the regulator for purposes such as power-up sequencing. the the regulator is enabled, there is typically a 300 ? s delay for waking up the bandgap refe rence. then the soft start-up begins. when the regulator is disabled, the p-mosfet is turned off immediately and the n-mosfet is turned on. thermal shut down the isl6273 has built-in thermal protection. when the internal temperature reaches 150c, the regulator is completely shut down. as the temperature d rops to 130c, the isl6273 resumes operation by steppi ng through a soft start-up. vcc by-passing the vcc is voltage is the supply to the internal control circui t and is derived from the pvin pin. an internal 10 ? resistor connects the two pins and also se rves as an filtering resistor. an external 0.1 ? f ceramic capacitor is recommended to by- pass the vcc supply.
isl6273 fn9256 rev 0.00 page 11 of 12 march 7, 2006 applications information output inductor and capacitor selection to consider state steady and transient operation, isl6273 typically uses a 1.8h output inductor. higher or lower inducto r value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple a nd output voltage ripple, the out put inductor value can be increased as shown in table 1. the inductor ripple current can be expressed as follows: the inductors saturation current rating needs be at least larg er than the peak current. the isl6 273 protects the peak current 2.1a. the saturation current n eeds be over 2.1a for maximum output current application. isl6273 uses internal compens ation network and the output capacitor value is dependant on the output voltage. the ceramic capacitor is recomm ended to be x5r or x7r. the recommended minimum output capa citor values are shown in table 1. in table 1, the minimum output c apacitor value is given for different output voltage to ma ke sure the whole converter system stable. due to the limitation on power dissipation when the regulator disable and discharge output c apacitor, there is the maximum output c apacitor value. t he maximum output capacitor value is variable wit h the output voltage. the plot curve is shown in figure 20. input capacitor selection the main functions for the in put capacitor are to provide decoupling of the par asitic inductance and to provide filtering function to prevent t he switching current flowing back to the battery rail. a 10 ? f x5r or x7r ceramic capacitor is a good starting point for the in put capacitor selection. output voltage setting resistor selection the resistors r2 and r3 shown in figure 16 set the output voltage for the adjustable vers ion. the output voltage can be calculated by: where the 0.8v is the referenc e voltage. the voltage divider consists of r2 and r3 increases the quiescent current by vo/(r2+r3) so larger resistanc e is desirable . on the other hand, the fb pin has l eakage current that will cause error in the output voltage set ting. the leakage current has a typical value of 0.1 ? a. to minimize the accuracy impact on the output voltage, select the r3 no larger than 200k ? . layout recommendation the layout is a very important converter design step to make sure the designed converter w orks well. for isl6273 buck converter, the power loop is composed of the output inductor l, the output capacitor c out , phase pin and pgnd pin. it is necessary to make the power l oop as small as possible. in order to make the output volt age regulate well and avoid the noise couple from the power l oop specially for pfm mode operation, sgnd pin should be connected with pgnd pin at the terminals of the load. the heat of the i c is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for emi performance. table 1. output capacitor value vs v out v out c out l 0.8v 10f 1.0h~2.2h 1.2v 10f 1.2h~2.2h 1.6v 10f 1.8h~2.2h 1.8v 10f 1.8h~3.3h 2.5v 10f 1.8h~3.3h 3.3v 6.8f 1.8h~4.7h 3.6v 4.7f 1.8h~4.7h ? i v o 1 v o v in --------- C ?? ?? ?? ? lf s ? -------------------------------------- - = 600 505 410 315 220 125 30 output capacitor value (f) 1.27 0.8 1.73 2.2 2.67 3.13 3.6 output voltage (v) figure 20. the maximum cap vs the output voltage v o 0.8 1 r 2 r 3 ------ - + ?? ?? ?? ? =
isl6273 fn9256 rev 0.00 page 12 of 12 march 7, 2006 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k 9 l m l10.3x3c 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.25 0.30 5, 8 d 3.00 bsc - d2 2.23 2.38 2.48 7, 8 e 3.00 bsc - e2 1.49 1.64 1.74 7, 8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n102 nd 5 3 rev. 0 3/05 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for dimensions e2 & d2.

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